Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured.
It is often desirable to include a microprocessor within an FPGA. The microprocessor, sometimes referred to as an embedded core, may be capable of defining its own peripheral logic by configuring a portion of the FPGA. However, some portion of the FPGA must be configured before the embedded microprocessor can operate and, in addition, a “boot code” that is initially executed by the embedded microprocessor may need to be loaded into memory. Consequently, the FPGA is configured in two stages, one before and one after the microprocessor is booted.
Several options currently exist for this two-phase configuration. External “configurator” logic may be used to transfer initial configuration data into the FPGA from a non-volatile memory. Such configurator logic, however, typically lies idle except for a few milliseconds during FPGA power-up. A master-serial mode technique may be employed to transfer initial configuration data into the FPGA. The master serial mode technique, however, uses an FPGA-specific serial programmable read-only memory (SPROM), which is costly and not easily updated by the embedded microprocessor. A master-SelectMap mode technique is, in effect, a byte-wide master-serial mode technique and suffers from similar drawbacks. A master-parallel mode technique requires the use of a large number of pins on the FPGA package that in many instances will not be reused after the initial configuration phase.
Therefore, there exists a need in the art for a configuration technique that does not require external configuration logic or other specialized circuitry commonly associated with the forgoing configuration techniques.